Performance Analysis of CMOS Inverter Using Sleepy Stack Power Dissipation

EasyChair Preprint 8262

Abstract

Scaling using the CMOS inverter techniques has improve performance and reduce power dissipation Two important characteristics of CMOS devices are high noise immunity and low static power consumption. In nanotechnology the power dissipation and various performance analysis have emerged as major design considerable. These may grow the problem continue with leakage power and become a fundamental problem of power consumption. To overcome the issue of deep submicron technology by seeing the report of to International Technology Roadmap for Semiconductors (ITRS), the total power dissipation may be significantly contributed by leakage power dissipation projected to go exponentially in next decades.to survey that support good performance, low dissipation in era of low consumption. Sleepy stack approach is a combination of two well-known low-leakage techniques: the forced stack and sleep transistor approach is very less as compared to other techniques. This paper represents performance analysis of CMOS inverter using sleepy stack power dissipation consume 50% less power as comparison to standard CMOS technique in 60nm technology

Keyphrases: CMOS inverter, forced stack, leakage power, low-power pipelined cache, power dissipation, sleepy stack

@booklet{EasyChair:8262,
  author    = {Mahima Yadav and Laxminarayan Gahalod and Soni Changlani},
  title     = {Performance Analysis of CMOS Inverter Using Sleepy Stack Power Dissipation},
  howpublished = {EasyChair Preprint 8262},
  year      = {EasyChair, 2022}}